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Introduction

The ECL (Esterel-C Language) project is a system-level specification research project originating at Cadence Berkeley Laboratories. The project began in 1996, was first released to the public in March 2000, and was put on sourceforge in March 2001.

ECL is a language and a corresponding compiler suite for functional specification of reactive embedded systems. It can be used either stand-alone or in combination with system-level design tools, such as Cadence's VCC tool exploration of hardware/software implementation tradeoffs, or the U.C. Berkeley freely downloadable POLIS tool.  For use with VCC, see the section in the documentation that accompanies ECL (ecl/doc/ecl_doc/*.tex).

Each ECL release contains the source code, regression tests, and LaTeX documentation.

Mini-FAQ

What is ECL? ECL is a language for embedded system specification. ECL stands for Esterel-C Language; the term is used both for the language and its compiler. The language is ANSI-C with added constructs inspired by Esterel for specifying reactivity (signal communication, pre-emption, and concurrency). It conveniently supports specification of mixed control/data modules. The compilation is performed by splitting the source code into reactive Esterel code and data-dominated C code. The reactive portion can be robustly optimized and synthesized to either hardware or software, while the C residual code must be implemented in software as is. ECL was developed by Luciano Lavagno, Roberto Passerone, and Ellen Sentovich.

How do I use ECL? Download the latest release, unzip and untar it. The documentation is in ecl_doc.ps, and it will step you through the installation and running of some test examples.

Can ECL be used with Cadence's Virtual Component Codesign (VCC) tool? Yes! There are specific instructions in the ECL documentation for importing ECL modules into VCC. For more information about VCC and purchasing licenses, see the VCC page. VCC is also part of the Cadence University program.

Are there any published papers?? Yes! A paper on ECL appeared in DAC 99. It is available for download in postscript from
http://ecl.sourceforge.net.

Questions or comments? Send mail to ecl-devel@lists.sourceforge.net.  

Project Goals

  • Combine the best features of the existing languages Esterel and C:
    • Esterel is synchronous language with nice high-level control constructs (signal communication, concurrency, pre-emption). It lacks rich data types/structures and support for non-reactive (data-driven) loops.
    • C has a large set of data types and is a commonly used language. It is not convenient for specification of reactive control and other specialized parts of embedded systems.
  • Use the existing compilers, which are very robust. ECL compilation parses the input and splits the ECL design:
    • The reactive part and the simplest reactive data computations are compiled by the CMA Esterel compiler.
    • The rest is compiled by a standard C compiler.
  • Take advantage of the fact that C is already widely used in the domain of designing reactive embedded systems.  ECL can help support import of legacy designs, but is more for the description of new, complex pieces of reactive real-time behavior.
  • Quickly build a usable input language and compiler for use in VCC.

An ECL module is compiled to a pure Esterel part and some C residue code. These together comprise a single reactive block. The Esterel part, which contains all reactive statements, is converted to a single extended FSM, and will have the most flexibility: one can choose a hardware or software implementation and explore tradeoffs between the two by estimating the size/speed of the resulting hardware/software. The (optional) C part, called by the extended FSM, contains all instantaneous loops, data type definitions, and those C constructs that have no equivalent in Esterel.

Since ECL supports full ANSI C, it handles pure C input and thus can import legacy code, with very small interface modifications (to make it reactive and use I/O ports rather than function arguments). Such code can later gradually be rewritten in a more reactive style, thereby taking advantage of the enhanced synthesis and optimization provided by the ECL flow. For example, one might take a protocol stack written in C and encapsulate only the top level in an ECL module.  During a subsequent refinement, the routines computing the CRC and transmitting bits can be converted into modules (by replacing function calls with event emissions, for example) and further synthesized: partitioned into HW/SW, optimized, and analyzed.

Notes on Languages

  • We strongly support the paradigm of combining existing, useful languages, and this can be extended far beyond simply Esterel and C (including Java, for example, as in Jester).
  • We do not purport ECL as the new, all-encompassing SLDL (system-level design language). Rather, we intend it to be one of a set of languages in an SLDL suite. ECL will be used in this suite for control-dominated behaviors.
  • In fact, it is possible that the elusive SLDL is something like a natural language at the highest level, with the first refinement to a suite of languages as mentioned above. The SLDL at the highest level will probably be non-deterministic (unlike Esterel, C, or ECL). The language suite for example may contain SystemC 2.0 at the top-level, with SpecC for specifying communication and ECL for specifying module behavior, and VHDL and Verilog at the hardware level. The parse tree for the system-level language is more likely to be a DAG.